
library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity Memory is
   port(CS, WE0, WE1: in bit; Clk: in bit;
        MAR,MDR_out: in unsigned(15 downto 0);
        Ready: out bit; Mem_out: out unsigned(15 downto 0));
end Memory;
--32767(65535)
architecture Internal of Memory is
    type RAMtype is array (0 to 256) of unsigned(7 downto 0);

   signal RAM1: RAMtype := (
  
   "00001000","00010011", -- 0 ADD R3, R1 ; add 2 registers
   "11111111","00010011", -- 2 ADD R3,#-1 ; add immediate
   
   "00110100","11010011", -- 4 RROT R3,#4
   "00010100","11010011", -- 6 LROT R3,#4
   "00100011","11010011", -- 8 RSHFL R3,#3
   --"00000011","11010011", -- 10 LSHF R3,#3
   --"01100010","11010011", -- 12 RSHFA R3,#2
   "10000000","01010011", -- 10 AND R3,#0 ; and immediate
   "11111111","00010011", -- 12 ADD R3,#-1 ; add immediate  
   
   --"01000000","11000000", --JMP itself
   "11111110","00001001", -- 14 BRn #-4
   "00000011","11010011", -- 16 LSHF R3,#3

   
  
   others => (others => '0'));--"01000000","00101000","00010000","00010001",

   signal output: unsigned(15 downto 0);
   signal count: integer range 0 to 4:=0;
   begin
   Mem_out <= "0000000000000000"  when CS = '0' --or (WE0 = '1' and WE1 = '1')
   else output;  
   --Ready <= '1';
   process(Clk)
   begin
      if Clk = '1' and Clk'event then         
         if CS = '1' then
             if WE0 = '1' then
                  RAM1(to_integer(MAR(15 downto 0))) <= MDR_out(7 downto 0); --even
             end if;
             if WE1 = '1' then
                  RAM1(to_integer(MAR(15 downto 0))) <= MDR_out(15 downto 8); --odd
             end if;
         end if;
         output <= RAM1(to_integer(MAR(15 downto 0))+1) 
                  & RAM1(to_integer(MAR(15 downto 0)));
        
      end if;
      --if Clk = '0' and Clk'event then
      --if count = 3 then
      --     count <= 0; Ready <= '1';
      --  else
      --     count <= count + 1; Ready <= '0';
      --  end if;
      --end if;
      
   end process;
end Internal;
